Professor Valeria Bertacco and other researchers at the University of Michigan have released two new software tools to aid in Network-on-Chip (NoC) research:
Developed by Dong-hyeon Park, Ritesh Parikh and Valeria Bertacco
A traffic generator designed to help Network-on-Chip researchers analyze their network interconnect designs when running heterogeneous workloads. Researchers are expected to use PacketGenie to generate traffic testbenches for the heterogeneous systems that they want to test and then use the generated testbench on a cycle-accurate network simulator, such as BookSim, to test their interconnect designs.
Developed by Vaibhav Gogte, Ritesh Parikh and Valeria Bertacco
A graphical visualization tool for analysis of Network-on-Chip systems. It provides a visual display of packet information generated during Network-on-Chip simulations, making the design analysis easier. It can accept a wide range of data associated with links, routers, and virtual channels to generate a graph that is intuitive, easy to navigate and flexible.