UCLA Professor Jason Cong delivered a keynote address at the IEEE International Symposium on Low Power Electronics and Design (ISLPED) 2014, in La Jolla, CA, on August 12. In his talk, "Accelerator-Rich Architectures — From Single-chip to Datacenters,” he suggested that future processor architectures will make extensive use of accelerators from single-chip implementation to datacenter-level integration.
Such accelerator-rich architectures (ARAs) present a fundamental departure from the classical von Neumann architecture, which emphasizes efficient sharing of the executions of different instructions on a common pipeline, providing an elegant solution when the computing resource is scarce. In contrast, the accelerator-rich architecture features heterogeneity and customization for energy efficiency, which is better suited for energy-constrained design where the silicon resource is abundant. He discussed the progress on developing such ARAs, including the use of composable accelerator building blocks, customizable memory and interconnect supports, and efficient compilation and runtime systems for ARAs at all levels.