The "Steep Transistors Workshop" will be held at the University of Notre Dame in Indiana, October 5 - 6, 2015. Postdoc researchers and graduate students are encouraged to participate. The workshop is being organized by the Center for Low Energy Systems Technology (LEAST) and the Energy Efficient Tunnel FET Switches and Circuits (E2 SWITCH). This is an invited meeting of the leading researchers in steep transistor development, including participants from Europe, Asia, and the U.S. The intent of the two-day meeting is to share progress, improve understanding, and assess directions.
Registration for this workshop is $210 before Sept. 15 and $300 after that date.
Steep transistors with subthreshold swings less than 60 mV/decade are attracting attention worldwide due to their promise to enable electronic systems operating at 300 mV and below. Interband tunneling or internal gain mechanisms in the gate enable the steep onset of current with gate voltage. This field has seen dramatic development over the last few years, however there is yet no consensus on materials or device architecture, and the mechanisms limiting current performance are the subject of wide study. There are an increasing number of projections about the application space for these transistors, which is now extending beyond digital into the analog domain.
This event is sponsored by the Semiconductor Research Corporation (SRC) and DARPA through the Semiconductor Technology Advanced Research Network (STARnet). Corporate sponsors are Global Foundries, IBM, Intel, Micron, Raytheon, Texas Instruments, and United Technologies.