Tool Developed by C-FAR Researchers Detects RISC-V Errors

Friday, April 14, 2017

TriCheck, a tool developed by a team of C-FAR researchers at Princeton University along with industry collaborators, has found a series of errors in the RISC-V instruction set and is prompting changes in the memory model specification. The team is led by Professor Margaret Martonosi and includes PhD Students Caroline Trippel and Yatin Manerkar.

The Princeton University website describes the project and its findings:

The researchers, testing a technique they created for analyzing computer memory use, found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that, if uncorrected, the problems could cause errors in software running on RISC-V chips. Officials at the RISC-V Foundation said the errors would not affect most versions of RISC-V but would have caused problems for higher-performance systems.

"Incorrect memory access orderings can result in software performing calculations using the wrong values," said Margaret Martonosi, the Hugh Trumbull Adams '35 Professor of Computer Science at Princeton and the leader of the Princeton team that also includes Ph.D. students Caroline Trippel and Yatin Manerkar. "These in turn can lead to hard-to-debug software errors that either cause the software to crash or to be vulnerable to security exploits. With RISC-V processors often envisioned as control processors for real-world physical devices (i.e., internet of things devices) these errors can cause unreliability or security vulnerabilities affecting the overall safety of the systems."

Krste Asanovic, the chair of the RISC-V Foundation, welcomed the researchers' contributions. He said the RISC-V Foundation has formed a working group, headed by Martonosi's former graduate student and co-researcher Daniel Lustig, to solve the memory-ordering problems. Asanovic, a professor of electrical engineering and computer science at the University of California-Berkeley, said the RISC-V project was looking for input from the design community to "fill the gaps and the holes and getting a spec that everyone can agree on."

"The goal is to ratify the spec in 2017," he said. "The memory model is part of that."

Asanovic is also a C-FAR researcher.

The team presented a paper April 10 on their work at the 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).